Transistor scaling has been enabled by pitch scaling and other factors. For example, current scaling elements mainly focus on items that impact foot-print of the transistors, such as gate pitch, channel length, spacer thickness, contact critical dimension (CD), metal pitches and, for advanced technology, fin pitch. However, as the transistor further scales down to a gate pitch of about 50 nm and beyond, different factors (other than foot-print) start to play more significant roles. For example, initial gate height at the 50 nm and beyond starts to play a significant role in scaling.
A large budget (thick layer) of ILD may be needed for the initial gate height due to oxide material loss during dummy gate removal processes, e.g., using DHF chemistries, and cleaning processes which may damage the surface of the ILD. Moreover, it may be necessary to etch the oxide ILD with a chemistry selective to a gate cap material (e.g., SiN material); however, the oxide etch selectivity is not very good which results in additional oxide loss. Accordingly, due to this material loss, the initial height of the replacement gate structure needs to be very tall, which can result in bending and other fabrication issues.